1. Field of the Invention
The present invention relates to a semiconductor storage device in which for example, redundancy addresses and data used to adjust the levels of various voltages generated inside chips are stored in memory cells as fuse data. Furthermore, the present invention relates to a non-volatile semiconductor storage device that reads the fuse data from the memory cells upon power-on.
2. Description of the Related Art
Semiconductor memories normally store, as fuse data, redundancy addresses and initial data required to adjust the levels of various voltages generated inside chips. Fuses that store fuse data include, for example, laser fuses that can be blown when irradiated with laser light, electric fuses that control a current conductive state by electrically breaking down a transistor or capacitor element, and ROM fuses that uses some memory cells as a fuse area. A ROM fuse is used for a non-volatile memory.
A non-volatile memory provided with a ROM fuse generates a power-on reset signal upon power-on. In response to the power-on reset signal, a reset operation is performed on all circuits inside chips which must be reset. Further, the fuse data stored in the ROM fuses are read and held by a latch circuit.
FIG. 1 shows variations in power voltage VCC and current consumption ICC in a non-volatile memory, in which a ROM read operation is performed to read the fuse data from ROM fuses and set it in a latch circuit. In the following example, in particular, a NAND flash memory will be described as a non-volatile memory.
When a power voltage VCC rises to reach a power-on detection level, a power-on detecting circuit outputs a power-on reset signal. The power-on reset signal is supplied to a ROM read control circuit. Furthermore, the ROM read control circuit outputs a ROM read activation signal to start a ROM read operation. The ROM read operation is exactly the same as a normal read operation except that an access region is a ROM fuse region and that the ROM read operation includes an operation of setting read ROM fuse data in a latch circuit of a peripheral logic circuit.
During a ROM read operation, current consumption has a large peak value during an initial stage of the read operation because bit lines must be precharged. Subsequently, during data set (latch), the current consumption has a uniform small value. That is, during a read operation, a large current of about several mA on the average flows because various voltage generating circuits operate including a booster circuit required for read operations. Once the read operation is completed, data sensed by a sense amplifier is transferred to the peripheral circuit, where it is latched. At this time, the booster circuit need not operate, thus reducing a value for current consumption.
The recent non-volatile memories are widely used as inexpensive mass memories partly because of the use of fine-grained elements. Thus, a plurality of, e.g. four or eight memory chips are accommodated in the same package.
In a non-volatile memory provided with a plurality of memory chips in this manner, when the power voltage rises, a power-on reset operation is performed concurrently in the individual memory chips. Accordingly, a ROM read operation for loading fuse data is performed concurrently in all memory chips. Subsequently, when a user inputs, for example, a read command to address a memory region of a particular memory chip, a normal read operation is performed.
The normal operation activated by a command input after the power-on reset operation does not create any problems because it is impossible that the plurality of chips operate simultaneously. However, with a ROM read operation, no external addresses are input, and the device is automatically activated upon power-on. Accordingly, a ROM read operation is started concurrently in the individual memory chips. Thus, if there are virtually no differences in power-on detection timing among the power-on detecting circuits in the individual memory chips, a ROM read operation is started concurrently in all memory chips. The current consumption during a ROM read operation increases simply by a factor of four or eight compared to a single memory chip.
That is, in the prior art, when a non-volatile memory is constructed using a plurality of memory chips, it consumes a large amount of current immediately after power-on. Accordingly, if the system does not have a sufficient power supply capability, a value for the power voltage may decrease. Thus, for a non-volatile memory using a plurality of memory chips, it is desirable to reduce current consumption immediately after power-on.